1. Field of the Invention
The present invention pertains generally to microelectronic devices, and specifically, to circuit and network configurations designed to reduce the harmful effects of electrostatic discharge in such devices. More particularly, the present invention relates circuit and network configurations and methods resistant to very fast electrostatic discharge events.
2. Description of the Related Art
Electrostatic Discharge (ESD) is a significant problem in microelectronic devices. ESD damage results from high voltage and/or current applied to the terminals of microelectronic devices by human or machine contact during device manufacturing, assembly transportation/storage or PC board mounting. The voltage and current spikes are typically of a very short duration and can cause breakdown of such devices, thus rendering them inoperable. This is a problem of increasing importance as smaller and smaller device dimensions render them more susceptible to damage.
To protect microelectronic devices from the harmful effects of ESD, dedicated ESD protection circuits are commonly employed. Typically, such circuits are designed to divert ESD pulses from the device without affecting its performance under normal operating conditions. The protection circuit itself should be able to survive the ESD pulse. Nonetheless, in practice ESD impulses often destroy both the protection circuit and the protected device, even with ESD protection devices designed using state-of-the-art methods.
One of the underlying reasons for failure of prior art ESD protection devices is that their design is based on an incomplete understanding of the mechanisms by which an ESD pulse destroys the device. It is commonly understood in the prior art that the damage due to ESD pulses happens via:                1. Electrical breakdown of electronic structure due to high current that changes operating characteristics of the device; followed by        2. Thermal breakdown, wherein the high temperature induced by the pulse causes local current instabilities (e.g. current filamentation) and consequently melting of the semiconductor, contacts and/or other elements of the device.        
For ESD protection circuits, it is the thermal breakdown that is typically used as the design criterion. However, experimental evidence indicates that there must exist other phenomena that contribute to failure of ESD protection circuits even before the melting point has been reached. This is confirmed by poor reliability and unpredictable performance of ESD protection circuits designed according to the prior art.
Accordingly, in view of the problems and deficiencies of the prior art, a need exists to improve the reliability and performance of ESD protection devices, and improve the survivability of microelectronic devices subjected to ESD events. In addition, it is important that such an improved approach be relatively inexpensive to implement.